4 Mb pseudo/virtually SRAM: S Yoshioka, Y Nagatoma, S Takahashi, S Miyamoto, M Uesugi (Oki Electr. Ind. Inc., Tokyo, Japan) 1987 IEEE International Solid State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition, New York, USA, 25–27 Feb. 1987 (Coral Gables FL, USA: Lewis Winner, Feb. 1987), pp. 20–21, 320–322. In German

A 32 b LISP processor: K Watanabe, A Ish

A 32 b LISP processor: K Watanabe, A Ishikawa, Y Yamada, Y Hibino (Electr. Commun. Labs., NTT, Tokyo, Japan) 1987 IEEE International Solid State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition, New York, USA, 25–27 Feb. 1987 (Coral Gables, FL, USA: Lewis Winner, Feb. 1987), pp.200–201, 401

📂 Article 📅 1988 🏛 Elsevier Science 🌐 English ⚖ 98 KB

A CMOS chip pair for digital TV: S Suzuk

A CMOS chip pair for digital TV: S Suzuki, K Kawai, K Muramatsu, T Makino, S Saji (Toshiba Microelectron. Center, Kawasaki, Japan) 1987 IEEE International Solid State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition, New York, USA, 25–27 Feb. 1987 (Coral Gables, FL, USA: Lewis Winner, Feb. 1987), pp. 204–205, 403

📂 Article 📅 1988 🏛 Elsevier Science 🌐 English ⚖ 95 KB

A 7 ns 128K multichip ECL RAM-with-logic

A 7 ns 128K multichip ECL RAM-with-logic module: M Iwabuchi, K Ogiue, K Nakamura, S Makagami, S Isomura, S Kuroda, S Kawashima (Hitachi Device Dev. Center, Tokyo, Japan) 1987 IEEE International Solid State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition, New York, USA, 25–27 Feb. 1987 (Coral Gables, FL, USA: Lewis Winner, Feb. 1987), pp. 226–227, 411

📂 Article 📅 1988 🏛 Elsevier Science 🌐 English ⚖ 91 KB

A 4-K byte/17-ns cache memory has been introduced to a 1.3 pm CMOS/bipolar macrocell library for VLSI computers. The memory includes an address translation function, which uses an MOS memory cell and a comparator merged with a bipolar sense amplifier to accelerate access time. (6 refs.)

A 120 ns 4 Mb CMOS EPROM: S Atsumi, S Ta

A 120 ns 4 Mb CMOS EPROM: S Atsumi, S Tanaka, S Saito, N Ohtsuka, N Matsukawa, S Mori, Y Kaneko, K Yoshikawa, J Matsunaga, T Iizuka (Toshiba Semicond. Dev. Eng. Lab., Kawasaki, Japan), N ARAI 1987 IEEE International Solid State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition, New York, USA, 25–27 Feb. 1987 (Coral Gables, FL, USA: Lewis Winner, Feb. 1987), pp. 74–75, 344

📂 Article 📅 1988 🏛 Elsevier Science 🌐 English ⚖ 91 KB

A 4-K byte/17-ns cache memory has been introduced to a 1.3 pm CMOS/bipolar macrocell library for VLSI computers. The memory includes an address translation function, which uses an MOS memory cell and a comparator merged with a bipolar sense amplifier to accelerate access time. (6 refs.)

Circuit technologies for 16 Mb DRAMs: T

Circuit technologies for 16 Mb DRAMs: T Mano, T Matsumura, J Yamada, J Inoue, S Nakajima, K Minegish, K Miura, T Matsuda, C Hashimoto, H Namatsu (NTT Electr. Commun. Lab., Kanagawa, Japan) 1987 IEEE International Solid State Circuits Confence. Digest of Technical Papers. ISSCC. First Edition, New York, USA, 25–27 Feb. 1987 (Coral Gables, FL, USA: Lewis Winner, Feb. 1987), pp.22–23, 323–324

📂 Article 📅 1988 🏛 Elsevier Science 🌐 English ⚖ 91 KB

A BiCMOS image signal processor with lin

A BiCMOS image signal processor with line memories: Y Kobayashi, T Fukushima, S Miura, M Kanasaki, K Hirasawa (Hitachi Res. Lab., Ibaraki, Japan), K Asada, J Ide, K Yamasaki, Y Tanihara 1987 IEEE International Solid State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition, New York, USA, 25–27 Feb. 1987 (Coral Gables, FL, USA: Lewis Winner, Feb. 1987), pp. 182–183, 392

📂 Article 📅 1988 🏛 Elsevier Science 🌐 English ⚖ 38 KB

✦ Synopsis