𝔖 Bobbio Scriptorium
✦   LIBER   ✦

A 120 ns 4 Mb CMOS EPROM: S Atsumi, S Tanaka, S Saito, N Ohtsuka, N Matsukawa, S Mori, Y Kaneko, K Yoshikawa, J Matsunaga, T Iizuka (Toshiba Semicond. Dev. Eng. Lab., Kawasaki, Japan), N ARAI 1987 IEEE International Solid State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition, New York, USA, 25–27 Feb. 1987 (Coral Gables, FL, USA: Lewis Winner, Feb. 1987), pp. 74–75, 344

Publisher
Elsevier Science
Year
1988
Tongue
English
Weight
91 KB
Volume
19
Category
Article
ISSN
0026-2692

No coin nor oath required. For personal study only.

✦ Synopsis

A 4-K byte/17-ns cache memory has been introduced to a 1.3 pm CMOS/bipolar macrocell library for VLSI computers. The memory includes an address translation function, which uses an MOS memory cell and a comparator merged with a bipolar sense amplifier to accelerate access time. (6 refs.)

📜 SIMILAR VOLUMES

A BiCMOS image signal processor with lin
A BiCMOS image signal processor with line memories: Y Kobayashi, T Fukushima, S Miura, M Kanasaki, K Hirasawa (Hitachi Res. Lab., Ibaraki, Japan), K Asada, J Ide, K Yamasaki, Y Tanihara 1987 IEEE International Solid State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition, New York, USA, 25–27 Feb. 1987 (Coral Gables, FL, USA: Lewis Winner, Feb. 1987), pp. 182–183, 392
📂 Article 📅 1988 🏛 Elsevier Science 🌐 English ⚖ 38 KB
A 533 K-transistor LISP processor chip:
A 533 K-transistor LISP processor chip: P W Bosshart, C R Hewes, M Chang, K Chau, C Hoac, T W Houston, V Kalyan, S L Lusky, S Mahant-Shetti, D J Matzke, K N Ruparel, C Shaw, T Sridhar, D Stark (Texas Instrum. Inc., Dallas, TX, USA) 1987 IEEE International Solid State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition, New York, USA, 25–27 Feb. 1987 (Coral Gables, Fl, USA: Lewis Winner, Feb. 1987), pp. 202–203, 402
📂 Article 📅 1988 🏛 Elsevier Science 🌐 English ⚖ 191 KB