A 4-K byte/17-ns cache memory has been introduced to a 1.3 pm CMOS/bipolar macrocell library for VLSI computers. The memory includes an address translation function, which uses an MOS memory cell and a comparator merged with a bipolar sense amplifier to accelerate access time. (6 refs.)
✦ LIBER ✦
A 32 b LISP processor: K Watanabe, A Ishikawa, Y Yamada, Y Hibino (Electr. Commun. Labs., NTT, Tokyo, Japan) 1987 IEEE International Solid State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition, New York, USA, 25–27 Feb. 1987 (Coral Gables, FL, USA: Lewis Winner, Feb. 1987), pp.200–201, 401
- Publisher
- Elsevier Science
- Year
- 1988
- Tongue
- English
- Weight
- 98 KB
- Volume
- 19
- Category
- Article
- ISSN
- 0026-2692
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