A 32 b microprocessor with on-chip 2 K byte instruction cache: M Horowitz, J L Hennessy, P Chow, P G Gulak, J M Acken, A Agarwal, C Chu S A McFarling, S A Przybylski, S Richardson, A Salz, R T Simoni, D C Stark, P Steenkiste, S W K Tjang, M J Wing (Stanford Univ. Center for Integrated Syst., CA, USA) 1987 IEEE International Solid State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition, New York, USA, 25–27 Feb. 1987 (Coral Gables, FL, USA: Lewis Winner, Feb. 1987), pp. 30–31, 328. In German

• Publisher: Elsevier Science
• Year: 1988
• Tongue: English
• Weight: 98 KB
• Volume: 19
• Category: Article
• ISSN: 0026-2692
• DOI: 10.1016/s0026-2692(88)80164-2

✦ Synopsis

tained on an 8.4 • 8.4 mm 2 die. The circuit has been designed for an operating frequency of 30 MHz under worst-case conditions. Architectural features include 32-32-b general-purpose registers, 48 or 64-b virtual addressing, and multiprocessor capability, including semaphore instructions and support for multiprocessor cache coherency algorithms.