𝔖 Bobbio Scriptorium
✦   LIBER   ✦

0.5-6 ghz low-voltage low-power mixer using a modified cascode topology in 0.18 μm cmos technology

✍ Scribed by Liang, K.-H.; Chang, H.-Y.

Book ID
114444061
Publisher
The Institution of Engineering and Technology
Year
2011
Tongue
English
Weight
566 KB
Volume
5
Category
Article
ISSN
1751-8725

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

A low-voltage 5.4 GHZ monolithic cascode
A low-voltage 5.4 GHZ monolithic cascode LNA using 0.18 um CMOS technology
✍ Baohong Liu; Junfa Mao 📂 Article 📅 2010 🏛 John Wiley and Sons 🌐 English ⚖ 191 KB

## Abstract This article presents a low‐voltage monolithic cascode LNA using 0.18‐um CMOS technology. Different from the stacked threshold voltage supply topology of conventional cascode LNA, this cascode LNA is designed as two cascaded stages for low‐voltage application. For the purpose of lowerin

A low power 20-GHz low-noise amplifier f
A low power 20-GHz low-noise amplifier fabricated using 0.18-μm CMOS technology
✍ J.-X. Liu; H.-C. Kuo; Y.-K. Chu; J.-F. Yeh; H.-R. Chuang 📂 Article 📅 2009 🏛 John Wiley and Sons 🌐 English ⚖ 536 KB

## Abstract A 20‐GHz CMOS low‐noise amplifier (LNA) fabricated with the 0.18 μm process is presented. This two‐stage cascaded common source LNA exhibits low power consumption with a satisfying performance such as overall gain and noise figure (NF). The measurement is performed on‐wafer. The 20‐GHz

A Q-band CMOS low-noise amplifier using
A Q-band CMOS low-noise amplifier using a low-voltage cascode in 0.13-μm CMOS technology
✍ Seong-Gwon Lee; Jong-Wook Lee 📂 Article 📅 2011 🏛 John Wiley and Sons 🌐 English ⚖ 638 KB

## Abstract A Q‐band low‐noise amplifier (LNA) suitable for low‐voltage operation is presented in this paper.The amplifier uses a low‐voltage cascode structure in the first stage of the amplifier and was fabricated using a 0.13‐μm RF CMOS process with eight layers of copper metallization. Low‐volta

A low voltage highly linear 24-GHz down
A low voltage highly linear 24-GHz down conversion mixer in 0.18-μm CMOS
✍ Masum Hossain; Brian M. Frank; Yahia M. Antar 📂 Article 📅 2007 🏛 John Wiley and Sons 🌐 English ⚖ 353 KB

## Abstract A K‐band low voltage, highly linear folded Gilbert cell mixer in 0.18‐μm CMOS is presented. An optimization technique been introduced which is particularly applicable to Gilbert cell type mixers. This technique has been experimentally verified with a down conversion mixer fabricated in

A 5.2-GHz low-power VCO in 0.18-μm CMOS
A 5.2-GHz low-power VCO in 0.18-μm CMOS process
✍ Sheng-Lyang Jang; Kuan-Chun Shen; Cheng-Chen Liu 📂 Article 📅 2009 🏛 John Wiley and Sons 🌐 English ⚖ 349 KB

## Abstract A 5.2 GHz, 0.43 V voltage‐controlled oscillator (VCO) is designed and implemented in a 0.18 μm CMOS 1P6M process. The designed circuit topology consists of two parallel LC resonators in series with the gates of negative differential resistance transistors. At the supply voltage of 0.43