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A low-voltage 5.4 GHZ monolithic cascode LNA using 0.18 um CMOS technology

✍ Scribed by Baohong Liu; Junfa Mao

Book ID
102517549
Publisher
John Wiley and Sons
Year
2010
Tongue
English
Weight
191 KB
Volume
53
Category
Article
ISSN
0895-2477

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✦ Synopsis

Abstract

This article presents a low‐voltage monolithic cascode LNA using 0.18‐um CMOS technology. Different from the stacked threshold voltage supply topology of conventional cascode LNA, this cascode LNA is designed as two cascaded stages for low‐voltage application. For the purpose of lowering the whole power dissipation while RF performances are not influenced, the current occupation is reduced by decreasing the channel width of the second NMOS. The whole circuit is implemented through TSMC 0.18‐um CMOS technology. Measurement results show that it can get 10.7‐dB gain and 2.6 dB NF at frequency of 5.4 GHz. The IIP3 is about −2.3 dBm. The supply voltage is only 0.7 V, and the whole power dissipation is 6.3 mW. © 2011 Wiley Periodicals, Inc. Microwave Opt Technol Lett 53:386–389, 2011; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.25733

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