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VLSI design of clustering analyser using systolic arrays

โœ Scribed by Lai, M.F.; Nakano, M.; Wu, Y.P.; Hsieh, C.H.


Book ID
114448182
Publisher
The Institution of Electrical Engineers
Year
1995
Tongue
English
Weight
501 KB
Volume
142
Category
Article
ISSN
1350-2387

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Simulation-based design of programmable
โœ R. Smith; G. Sobelman ๐Ÿ“‚ Article ๐Ÿ“… 1991 ๐Ÿ› Elsevier Science ๐ŸŒ English โš– 613 KB

The paper describes how a simulator is used interactively to design programmable systolic arrays for use in signal-processing applications. A preliminary architecture is defined, with the algorithms targeted for implementation as the starting point. Hardware resources such as maths chips, controller