The paper describes how a simulator is used interactively to design programmable systolic arrays for use in signal-processing applications. A preliminary architecture is defined, with the algorithms targeted for implementation as the starting point. Hardware resources such as maths chips, controllers and memory are then selected. These hardware resources impose constraints on the design. The goal is then that of implementing the desired architecture using the selected hardware. A simulator is described that is used to model and examine architectural and algorithmic options. Via this analysis of the architecture and algorithms, the design can be optimized for a set of applications. The use of the simulator in an actual design is discussed.
systofic arrays, signal processing, simulation, algorithms, electronics design
The concept of systolic arrays was introduced by H T Kung in 19781. The term 'systolic' comes from the synchronous data communications used in systolic arrays. In Reference 1, Kung describes several features of systolic arrays:
โข The data and control flows are simple and regular.
This enables the design to be modular and scalable. โข The design uses extensive concurrency. The high performance of systolic arrays comes from the concurrent use of many simple cells. โข There are only a few types of simple cells. This helps the designer to exploit VLSI by replicating the same cell many times. โข Each data input is used many times. This allows for high throughput with modest I/O bandwidth.
These features allow systolic arrays to be implemented with the use of VLSI chips. Systolic arrays can use bit-serial, bit-parallel, floating-point or fixed-point arithmetic. Common array topologies proposed include linear arrays, 2D meshes, hexagonal arrays and tree structures. A simple example is a 3-cell linear systolic array used to execute a 3-point linear convolution.