The prospect of realizing nanometer-channel-length thin-film transistors (TFTs) for active matrix addressed pixelated arrays opens up a plethora of new high-performance applications, [1,2] in which the most amenable device topology is the vertical TFT (VTFT) in view of its small area. Previous attempts at fabricating VTFTs have yielded devices with high drain-leakage current, low on/off current ratio, and absence of saturation behavior at high drain voltages, all induced by short channel effects. [3,4] To overcome these adversities, which become dominant as the channel lengths approach the nanoscale regime, reduction of gate dielectric thickness is mandatory. However, the main problem with reducing the gate-dielectric thickness is the high gate-leakage current and, more importantly, early dielectric breakdown, which deteriorate device performance and reliability. [5,6] In VTFTs, the source and drain electrodes are vertically stacked together, separated by an intermediate insulator layer, and the channel is formed on the vertical sidewall of the source/insulator/ drain stack (see Fig. 1a andb). Since the thickness of the intermediate insulator layer defines the channel length, this can now be accurately controlled at the nanometer scale via the thickness of the insulator layer, without resorting to nanoscale lithography as would have been otherwise needed with lateral TFTs.
This communication reports on short-channel VTFTs, which yield excellent saturation characteristics, by virtue of the ultrathin silicon nitride (SiN x ) gate dielectric. Reliable ultrathin SiN x remains a key challenge for development of the next generation of nanometer channel-length transistors. While there have been previous attempts to deposit thin and functional SiN x , the techniques used are not compatible with standard TFT fabrication processes. [7,8] Here, we developed ultrathin SiN x using plasma-enhanced chemical vapor deposition (PECVD), whereby a dielectric thickness of mere 50 nm yields a leakage current of 0.1 nA cm Γ2 and breakdown electric field of 5.6 MV cm Γ1 . The fabricated transistors have a channel length (L) of 500 nm, and device area of 10 mm Γ 4 mm for a channel aspect ratio of 20, considering 2 mm minimum feature size.
To address the impact of thickness on the physical and electrical properties of the SiN x , we considered a metal/SiN x / metal structure with different thicknesses of SiN x . Silicon nitrides are generally deposited with a gas mixture SiH 4 /NH 3 (ratio of 1/20) [9] using PECVD. While this yields a very-high-quality film in terms of low leakage current and high breakdown voltage, it is only so for film thicknesses above 200 nm. [10] Hereafter in this article, the SiN x deposited by the aforementioned gas mixture will be referred to as conventional SiN x .