Compatibility of silicon gates with hafnium-based gate dielectrics

✍ Scribed by D.C. Gilmer; R. Hegde; R. Cotton; J. Smith; L. Dip; R. Garcia; V. Dhandapani; D. Triyoso; D. Roan; A. Franke; R. Rai; L. Prabhu; C. Hobbs; J.M. Grant; L. La; S. Samavedam; B. Taylor; H. Tseng; P. Tobin

• Publisher: Elsevier Science
• Year: 2003
• Tongue: English
• Weight: 429 KB
• Volume: 69
• Category: Article
• ISSN: 0167-9317
• DOI: 10.1016/s0167-9317(03)00290-9

✦ Synopsis

Silicon gate compatibility problems with hafnium-based gate dielectrics are reported. It generally can be stated that chemical vapor deposition (CVD) silicon gates using silane deposited directly onto polycrystalline HfO at conventional 2 temperatures (near 620 8C) results in (1) a low density of large inhomogeneous polycrystalline-silicon (poly-Si) grains, (2) electrical properties much worse compared to similar HfO films using metal gates or silicon gates with low temperature 2 deposition. However, depositing conventional CVD poly-Si gates directly onto Al O -capped, hafnium-silicate-capped, or 2 3 physical vapor deposition (PVD) silicon-capped HfO resulted in the absence of large inhomogeneous poly-Si grains and 2 3 well behaved capacitors with leakage reduction greater than 10 times compared to the poly-Si / HfO and poly-Si / SiO 2 2 controls of similar electrical thickness. The two observed adverse phenomena for conventional poly-Si deposited directly on HfO are attributed to a partial reduction of the HfO by the poly-Si deposition ambient. In the first case (1) the partial 2 2 reduction occurs locally on the HfO surface, forming Hf-Si bond(s) which act as nucleation points for crystalline silicon 2 x

growth while in the second case (2) the partial reduction occurs along grain boundaries resulting in electrical traps that increase film leakage. In addition, it is postulated that similar adverse interactions with conventionally deposited CVD poly-Si may occur with any transition metal oxide whose metal can form stable silicides.