✦ LIBER ✦

Testability and path testing strategies

✍ Scribed by Giovanni Cantone; Aniello Cimitile; Ugo de Carlini

Publisher: Elsevier Science
Year: 1987
Weight: 784 KB
Volume: 21
Category: Article
ISSN: 0165-6074
DOI: 10.1016/0165-6074(87)90065-2

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

VLSI testing and testability

✍ István Erényi 📂 Article 📅 1993 🏛 Elsevier Science ⚖ 70 KB

VLSI testing and testability considerati

VLSI testing and testability considerations: an overview

✍ S.L. Hurst 📂 Article 📅 1988 🏛 Elsevier Science 🌐 English ⚖ 868 KB

The increasing capability of being able to fabricate a very large number of transistors on a single integrated-circuit chip and the complexity of the possible systems has increased the importance of being able to test such circuits in an acceptable way and in an acceptable time. The time difficultie

Assignment and allocation of highly test

Assignment and allocation of highly testable data paths under scan optimization

✍ Asad A. Ismaeel; M.K. Dhodhi; Rajan Mathew 📂 Article 📅 1996 🏛 Elsevier Science 🌐 English ⚖ 933 KB

This paper addresses the synthesis of highly testable data paths under scan optimization from a given scheduled data flow graph. The synthesis uses an intelligent register allocation technique to minimize the number of sequential loops. Sequential loops in a data path cause poor testability and the

Design for electron beam testability: On

Design for electron beam testability: On-chip generation of periodic test sequences in a scan path environment

✍ Josef Groβ; Torsten Grüning 📂 Article 📅 1992 🏛 Elsevier Science 🌐 English ⚖ 873 KB

CMOS fault modeling, test generation and

CMOS fault modeling, test generation and design for testability

✍ C Matthäus; B Krüger-Sprengel; C Glowacz; U Hübner; H.T Vierhaus 📂 Article 📅 1988 🏛 Elsevier Science ⚖ 406 KB

Logic Testing and Design for testability

Logic Testing and Design for testability: Hideo Fujiwara, MIT Press (1985)

📂 Article 📅 1986 🏛 Elsevier Science 🌐 English ⚖ 112 KB