VLSI testing and testability considerations: an overview

✍ Scribed by S.L. Hurst

• Publisher: Elsevier Science
• Year: 1988
• Tongue: English
• Weight: 868 KB
• Volume: 19
• Category: Article
• ISSN: 0026-2692
• DOI: 10.1016/s0026-2692(88)80045-4

✦ Synopsis

The increasing capability of being able to fabricate a very large number of transistors on a single integrated-circuit chip and the complexity of the possible systems has increased the importance of being able to test such circuits in an acceptable way and in an acceptable time. The time difficulties of tests are primarily due to the limited number of input/output connections on a chip which is the only means of access to the circuit, the ratio of the number of gates on a chip to the number of accessible I/Os increasing with chip size.

In this overview we will consider the difficulties and the present methods adopted to make the problem manageable. This must involve a consideration of the testability of the circuit at the design stage, with some partitioning and structured design methodology essential in the case of very complex circuits.