Assignment and allocation of highly testable data paths under scan optimization
✍ Scribed by Asad A. Ismaeel; M.K. Dhodhi; Rajan Mathew
- Publisher
- Elsevier Science
- Year
- 1996
- Tongue
- English
- Weight
- 933 KB
- Volume
- 21
- Category
- Article
- ISSN
- 0167-9260
No coin nor oath required. For personal study only.
✦ Synopsis
This paper addresses the synthesis of highly testable data paths under scan optimization from a given scheduled data flow graph. The synthesis uses an intelligent register allocation technique to minimize the number of sequential loops. Sequential loops in a data path cause poor testability and the complexity of test generation grows exponentially with the number of sequential loops. The register allocation technique also identifies certain registers in the synthesized data path as scan registers to break the sequential loops. The synthesis also uses an interconnect allocation scheme which optimizes for the number of multiplexer inputs. Our main objective is to eliminate or minimize the number of sequential loops and to identify minimum number of scan registers to break these loops. Thus, the synthesized data path is free of sequential loops, highly testable and has a low scan register cost overhead. Our technique is verified on different benchmark examples and the results are promising.