✦ LIBER ✦

Test generation for pattern-sensitive faults in integrated switches

✍ Scribed by Tyszer, J.

Book ID: 117860479
Publisher: IEEE
Year: 1991
Tongue: English
Weight: 315 KB
Volume: 39
Category: Article
ISSN: 0090-6778
DOI: 10.1109/26.111431

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

Test pattern generation for droop faults

✍ Mitra, D.; Sur-Kolay, S.; Bhattacharya, B.B.; Kundu, S.; Nigam, A.; Dey, S.K. 📂 Article 📅 2010 🏛 The Institution of Engineering and Technology 🌐 English ⚖ 569 KB

Test Pattern Generation for API Faults i

Test Pattern Generation for API Faults in RAM

✍ Saluja, K.K.; Kinoshita, K. 📂 Article 📅 1985 🏛 IEEE 🌐 English ⚖ 805 KB

Automatic Test Pattern Generation for Re

Automatic Test Pattern Generation for Resistive Bridging Faults

✍ Piet Engelke; Ilia Polian; Michel Renovell; Bernd Becker 📂 Article 📅 2006 🏛 Springer US 🌐 English ⚖ 509 KB

Distributed Test Pattern Generation for

Distributed Test Pattern Generation for Stuck-At Faults in Sequential Circuits

✍ Peter A. Krauss; Andreas Ganz; Kurt J. Antreich 📂 Article 📅 1997 🏛 Springer US 🌐 English ⚖ 258 KB

Test pattern generation for crosstalk fa

Test pattern generation for crosstalk faults considering the gate delay

✍ Noriyoshi Itazaki; Kozo Kinoshita; Hisao Naitoh 📂 Article 📅 1995 🏛 John Wiley and Sons 🌐 English ⚖ 727 KB

Generic DFT approach for pattern sensiti

Generic DFT approach for pattern sensitive faults in word-oriented memories

✍ Amin, A.A.; Hamzah, A.A.; Abdel-Aal, R.E. 📂 Article 📅 1996 🏛 The Institution of Electrical Engineers 🌐 English ⚖ 457 KB