๐”– Bobbio Scriptorium
โœฆ   LIBER   โœฆ

Test for detection and location of intermittent faults in combinational circuits

โœ Scribed by Ismaeel, A.A.; Bhatnagar, R.

Book ID
114555649
Publisher
IEEE
Year
1997
Tongue
English
Weight
474 KB
Volume
46
Category
Article
ISSN
0018-9529

No coin nor oath required. For personal study only.

๐Ÿ“œ SIMILAR VOLUMES

Identification of redundant faults in co
Identification of redundant faults in combinational circuits
โœ Tetsuro Minamiyama; Yuzo Takamatsu ๐Ÿ“‚ Article ๐Ÿ“… 2000 ๐Ÿ› John Wiley and Sons ๐ŸŒ English โš– 161 KB ๐Ÿ‘ 2 views

An efficient redundant-fault identification method is useful for test pattern generation. The authors earlier proposed a method for redundant fault identification of combinational circuits that consisted of the procedures regarding the fan-out stems used in the FIRE algorithm and the analysis of ta

Modeling and testing for stuck faults in
Modeling and testing for stuck faults in BiCMOS combinational circuits
โœ Asad A. Ismaeel; Rakesh Bhatnagar ๐Ÿ“‚ Article ๐Ÿ“… 1997 ๐Ÿ› Elsevier Science ๐ŸŒ English โš– 968 KB

A transistor level model and a testing methodology are presented for BiCMOS circuits. The model fully describes the functional (logical) grad parametric behavior of the 13iCMOS circuits in the presence of transistor stuck faults. Tile model employs the logic transistor function (LTF). The LTF descri