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SPIE Proceedings [SPIE SPIE's 27th Annual International Symposium on Microlithography - Santa Clara, CA (Sunday 3 March 2002)] Metrology, Inspection, and Process Control for Microlithography XVI - Gate line-edge roughness effects in 50-nm bulk MOSFET devices

✍ Scribed by Xiong, Shiying; Bokor, Jeffrey; Xiang, Qi; Fisher, Philip; Dudley, Ian M.; Rao, Paula; Herr, Daniel J. C.

No coin nor oath required. For personal study only.

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