As the feature size of integrated circuits is driven to smaller dimensions the importance of the inter-and intralayer isolator capacitance in future metallization schemes becomes more pronounced. Organic polymers with low dielectric constants are one class of material choice for the replacement of SiO . However, their successful integration into functional circuits 2 requires new fabrication procedures. The embedded dielectric scheme offers an evolutionary path for their successful integration into a subtractive etched, aluminum-based integrated circuit. This scheme can effectively lower the total capacitance while minimally changing the rest of the metallization fabrication process. However, the non-conformal deposition of spin-on polymers requires an effective planarization process. Therefore, this paper focuses on the planarization capability of a chemical mechanical polishing process (CMP) using SiLK resin as the interlayer dielectric material. The experimental results demonstrate the high planarization capability of the CMP process using a commercially available slurry. The post-CMP degree of planarization is greater than 95% for all feature dimensions and this planarity can be achieved rapidly. SiLK dielectric coatings are therefore considered as a promising candidate to replace SiO in existing Al / W-based