Shallow source-drain structures for VLSI CMOS technology

✍ Scribed by AL Butler; DJ Foster

• Publisher: Elsevier Science
• Year: 1985
• Weight: 220 KB
• Volume: 129
• Category: Article
• ISSN: 0378-4363
• DOI: 10.1016/0378-4363(85)90582-0

✦ Synopsis

This paper proposes an improved CMOS source-drain technique which employs amorphising silicon implants prior to dopant implantation to eliminate ion channelling and platinum silicidation to substantially reduce sheet resistance. Counterdoping of the p+ regions by high concentration arsenic implantation is used to enable both NMOS and PMOS devices to be manufactured with only one photolithographic masking operation. The technique has been incorporated into a VLSI CMOS process schedule at our laboratories.