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RIE lag in high aspect ratio trench etching of silicon

✍ Scribed by Henri Jansen; Meint de Boer; Remco Wiegerink; Niels Tas; Edwin Smulders; Christina Neagu; Miko Elwenspoek


Publisher
Elsevier Science
Year
1997
Tongue
English
Weight
552 KB
Volume
35
Category
Article
ISSN
0167-9317

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✦ Synopsis


While etching high aspect ratio trenches into silicon with reactive ion etching (POE) using an SFJO2 chemistry it is observed that the etch rate is depending on the mask opening. This effect is known as POE lag and is caused by the depletion of etching ions and radicals or inhibiting neutrals during their trench passage. In order to decide which source is the main cause, we constructed special "horizontal trenches" where only radicals are controlling the etching. The experiment showed that radicals are not responsible for POE lag. Inhibitor depletion will result in inverse POE lag. This effect is not found during our experimentation which leaves us with ion depletion to explain POE lag. Depletion of ions is caused by ions captured by the sidewalls due to the angular distribution of incoming ions into the trench opening and the deflection of ions in the trench due to electrostatic fields• The analysis given in this paper indicates that the influencing field causes ion deflection, ion depletion, and therefore POE lag in micron-sized Si trenches for low-energetic ions• In all cases, thus independent of the feature size, the angular distribution of incoming ions is thought to have a major contribution to RIE lag at higher pressures. These phenomena will be treated theoretically and simulated using a program, written in c++ under windows, in order to give a quantitative analysis of RIE lag.


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