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[IEEE IEEE International Electron Devices Meeting - San Francisco, CA, USA (8-11 Dec. 2002)] Digest. International Electron Devices Meeting, - A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 μm/sup 2/ SRAM cell

✍ Scribed by Thompson, S.; Anand, N.; Armstrong, M.; Auth, C.; Arcot, B.; Alavi, M.; Bai, P.; Bielefeld, J.; Bigwood, R.; Brandenburg, J.; Buehler, M.; Cea, S.; Chikarmane, V.; Choi, C.; Frankovic, R.; Ghani, T.; Glass, G.; Han, W.; Hoffmann, T.; Hussein, M.; Jacob, P.; Jain, A.; Jan, C.; Joshi, S.; Kenyon, C.; Klaus, J.; Klopcic, S.; Luce, J.; Ma, Z.; Mcintyre, B.; Mistry, K.; Murthy, A.; Nguyen, P.; Pearson, H.; Sandford, T.; Schweinfurth, R.; Shaheed, R.; Sivakumar, S.; Taylor, M.; Tufts, B.; Wallace, C.; Wang, P.; Weber, C.; Bohr, M.

Book ID: 115484980
Publisher: IEEE
Year: 2002
Weight: 276 KB
Volume: 0
Category: Article
ISBN-13: 9780780374621
DOI: 10.1109/iedm.2002.1175779

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