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[IEEE 2008 IEEE International Electron Devices Meeting (IEDM) - San Francisco, CA, USA (2008.12.15-2008.12.17)] 2008 IEEE International Electron Devices Meeting - A 32nm logic technology featuring 2nd-generation high-k + metal-gate transistors, enhanced channel strain and 0.171μm2 SRAM cell size in a 291Mb array

✍ Scribed by Natarajan, S.; Armstrong, M.; Bost, M.; Brain, R.; Brazier, M.; Chang, C.-H.; Chikarmane, V.; Childs, M.; Deshpande, H.; Dev, K.; Ding, G.; Ghani, T.; Golonzka, O.; Han, W.; He, J.; Heussner, R.; James, R.; Jin, I.; Kenyon, C.; Klopcic, S.; Lee, S.-H.; Liu, M.; Lodha, S.; McFadden, B.; Murthy, A.; Neiberg, L.; Neirynck, J.; Packan, P.; Pae, S.; Parker, C.; Pelto, C.; Pipes, L.; Sebastian, J.; Seiple, J.; Sell, B.; Sivakumar, S.; Song, B.; Tone, K.; Troeger, T.; Weber, C.; Yang, M.; Yeoh, A.; Zhang, K.

Book ID: 121673252
Publisher: IEEE
Year: 2008
Weight: 503 KB
Category: Article
ISBN: 1424423775
DOI: 10.1109/IEDM.2008.4796777

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