𝔖 Bobbio Scriptorium

✦ LIBER ✦

[IEEE Comput. Soc 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Boston, MA, USA (3-5 Nov. 2003)] Proceedings. 16th IEEE Symposium on Computer Arithmetic - Heterogeneous redundancy for fault and defect tolerance with complexity independent area overhead

✍ Scribed by Kumar, V.V.; Lach, J.

Book ID: 118129434
Publisher: IEEE Comput. Soc
Year: 2003
Weight: 225 KB
Volume: 0
Category: Article
ISBN-13: 9780769520421
DOI: 10.1109/dftvs.2003.1250157

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

[IEEE Comput. Soc 18th IEEE Internationa

[IEEE Comput. Soc 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Boston, MA, USA (3-5 Nov. 2003)] Proceedings. 16th IEEE Symposium on Computer Arithmetic - Dependability analysis using a fault injection tool based on synthesizability of HDL models

✍ Zarandi, H.R.; Miremadi, S.G.; Ejlali, A. 📂 Article 📅 2003 🏛 IEEE Comput. Soc ⚖ 299 KB

[IEEE Comput. Soc 18th IEEE Internationa

[IEEE Comput. Soc 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Boston, MA, USA (3-5 Nov. 2003)] Proceedings. 16th IEEE Symposium on Computer Arithmetic - A tool for injecting SEU-like faults into the configuration control mechanism of Xilinx Virtex FPGAs

✍ Alderighi, M.; Casini, F.; D'Angelo, S.; Mancini, M.; Marmo, A.; Pastore, S.; Se 📂 Article 📅 2003 🏛 IEEE Comput. Soc ⚖ 538 KB

[IEEE Comput. Soc 20th IEEE Internationa

[IEEE Comput. Soc 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Monterey, CA, USA (3-5 Oct. 2005)] 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05) - Computing cache vulnerability to transient errors and its implication

✍ Wei Zhang, 📂 Article 📅 2005 🏛 IEEE Comput. Soc ⚖ 236 KB

[IEEE Comput. Soc 17th IEEE Internationa

[IEEE Comput. Soc 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. DFT 2002 - Vancouver, BC, Canada (6-8 Nov. 2002)] 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings. - Fault-tolerant CAM architectures: a design framework

✍ Salice, F.; Sami, M.G.; Stefanelli, R. 📂 Article 📅 2002 🏛 IEEE Comput. Soc 🌐 English ⚖ 426 KB

[IEEE Comput. Soc 20th IEEE Internationa

[IEEE Comput. Soc 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Monterey, CA, USA (3-5 Oct. 2005)] 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05) - Soft error modeling and protection for sequential elements

✍ Asadi, H.; Tahoori, M.B. 📂 Article 📅 2005 🏛 IEEE Comput. Soc ⚖ 258 KB

[IEEE Comput. Soc 20th IEEE Internationa

[IEEE Comput. Soc 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Monterey, CA, USA (3-5 Oct. 2005)] 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05) - Multiple transient faults in logic: an issue for next generation ICs?

✍ Rossi, D.; Omana, M.; Toma, F.; Metra, C. 📂 Article 📅 2005 🏛 IEEE Comput. Soc ⚖ 285 KB