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[IEEE 2010 17th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2010) - Singapore, Singapore (2010.07.5-2010.07.9)] 2010 17th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits - ESD protection design for low trigger voltage and high latch-up immunity

✍ Scribed by Tseng, Jen-Chou; Hsu, Chung-Ti; Tsai, Chia-Ku; Yu-Ching Liao, ; Ker, Ming-Dou

Book ID: 126645812
Publisher: IEEE
Year: 2010
Weight: 606 KB
Category: Article
ISBN: 1424455960
DOI: 10.1109/IPFA.2010.5532307

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