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[IEEE 2009 International Symposium on VLSI Technology, Systems, and Applications (VLSI-TSA) - Hsinchu, Taiwan (2009.04.27-2009.04.29)] 2009 International Symposium on VLSI Technology, Systems, and Applications - FinFET resistance mitigation through design and process optimization

✍ Scribed by Wang, Cindy; Chang, Josephine; Lin, Chung-Hsun; Kumar, Arvind; Gehring, Andreas; Cho, Jin; Majumdar, Amlan; Bryant, Andreas; Ren, Zhibin; Chan, Kevin; Kanarsky, Thomas; Wang, Xinlin; Dokumaci, Omer; Guillorn, Michael; Khater, Marwan; Yang, Qingyun; Li, Xi; Naeem, Munir; Holt, Judson; Moon, Yongsik; King, John; Yates, John; Zhang, Ying; Park, Dae-gyu; Ouyang, Christine; Haensch, Wilfried

Book ID: 120177814
Publisher: IEEE
Year: 2009
Weight: 372 KB
Category: Article
ISBN: 1424427843
DOI: 10.1109/VTSA.2009.5159323

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