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Design and optimization of a low-power and very-high-performance 0.25 μm advanced pnp bipolar process

✍ Scribed by Boualem Djezzar

Book ID: 104157816
Publisher: Elsevier Science
Year: 1998
Tongue: English
Weight: 432 KB
Volume: 29
Category: Article
ISSN: 0026-2692
DOI: 10.1016/s0026-2692(97)00018-9

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✦ Synopsis

The low-power and very-high-performance 0.25/~m vertical pnp bipolar process is designed and characterized by using the mixed two-dimensional numerical device/circuit simulator (CODECS). This pnp transistor has a 25 nmwide emitter, a 38 nm-wide base region, a current gain of 17 (without poly-Si emkter effect) and maximum cut-off ~equency of 24GHz. The conventional ECL circuit, designed by this pnp tr-,msistor, exhibits an unloaded gate delay of 22psec at 1.75mW, and a delay time less than 16psec/stage for an unloaded ECL ring-oscillator.

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