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Compact Modeling and Simulation of Circuit Reliability for 65-nm CMOS Technology

โœ Scribed by Wenping Wang, ; Reddy, V.; Krishnan, A.T.; Vattikonda, R.; Krishnan, S.; Yu Cao,


Book ID
120043103
Publisher
IEEE
Year
2007
Tongue
English
Weight
370 KB
Volume
7
Category
Article
ISSN
1530-4388

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We have developed low standby power (LSTP) FET utilizing HfSiON dielectric. Due to optimizations of channel and offset spacer structure, we could put threshold voltage of pFET into the place of LSTP region, working through the Fermilevel-pinning effect. This resulted in the reduction of propagation