New Design of 2 VDD-Tolerant Power-Rail ESD Clamp Circuit for Mixed-Voltage I/O Buffers in 65-nm CMOS Technology

✍ Scribed by Chih-Ting Yeh; Ming-Dou Ker

• Book ID: 114614435
• Publisher: Institute of Electrical and Electronics Engineers
• Year: 2012
• Tongue: English
• Weight: 309 KB
• Volume: 59
• Category: Article
• ISSN: 1549-7747
• DOI: 10.1109/tcsii.2012.2184372