𝔖 Bobbio Scriptorium

✦ LIBER ✦

Design of 2VDD-Tolerant Power-Rail ESD Clamp Circuit With Consideration of Gate Leakage Current in 65-nm CMOS Technology

✍ Scribed by Chang-Tzu Wang; Ming-Dou Ker

Book ID: 114619992
Publisher: IEEE
Year: 2010
Tongue: English
Weight: 851 KB
Volume: 57
Category: Article
ISSN: 0018-9383
DOI: 10.1109/ted.2010.2046457

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

New Design of 2 VDD-Tolerant Power-Rail

New Design of 2 VDD-Tolerant Power-Rail ESD Clamp Circuit for Mixed-Voltage I/O Buffers in 65-nm CMOS Technology

✍ Chih-Ting Yeh; Ming-Dou Ker 📂 Article 📅 2012 🏛 Institute of Electrical and Electronics Engineers 🌐 English ⚖ 309 KB

[IEEE 2013 IEEE International Symposium

[IEEE 2013 IEEE International Symposium on Circuits and Systems (ISCAS) - Beijing (2013.5.19-2013.5.23)] 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013) - Low-leakage power-rail ESD clamp circuit with gated current mirror in a 65-nm CMOS technology

✍ Altolaguirre, Federico A.; Ming-Dou Ker, 📂 Article 📅 2013 🏛 IEEE ⚖ 448 KB