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Analysis and Modeling of Threshold Voltage Mismatch for CMOS at 65 nm and Beyond

โœ Scribed by Johnson, J.B.; Hook, T.B.; Yoo-Mi Lee


Book ID
115543244
Publisher
IEEE
Year
2008
Tongue
English
Weight
365 KB
Volume
29
Category
Article
ISSN
0741-3106

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We have developed low standby power (LSTP) FET utilizing HfSiON dielectric. Due to optimizations of channel and offset spacer structure, we could put threshold voltage of pFET into the place of LSTP region, working through the Fermilevel-pinning effect. This resulted in the reduction of propagation