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Built-in self test of S2I switched current circuits

โœ Scribed by Geir E. Sether; Chris Toumazou; Gaynor Taylor; Kevin Eckersall; Ian M. Bell

Publisher
Springer
Year
1996
Tongue
English
Weight
475 KB
Volume
9
Category
Article
ISSN
0925-1030

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โœฆ Synopsis

This article presents a new concept for built-in self test of switched current circuits based on $2I memory cells. From the spectrum of possible transistor defects reported in CMOS processes [2], five different faultsituations were modelled and the ability to detect the various failures was studied. This was accomplished by simulating a simple switched-current integrator in which all the different failures were introduced sequentially in all transistors. The fault coverage was derived and the result shows that a powerful system for detection of transistor faults in an analogue sampled-data system can be readily realised with a minimum of additional overhead circuitry.

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โœ Yukiya Miura; Yasushi Wada; Kozo Kinoshita ๐Ÿ“‚ Article ๐Ÿ“… 1993 ๐Ÿ› John Wiley and Sons ๐ŸŒ English โš– 736 KB

## Abstract Recently current testing is beginning to be noticed as a testing method for CMOS circuits. However, since CMOS circuits cause the dynamic current due to switching, it has been pointed out that testing at a fast clock rate by current testing is difficult. To cope with this problem a buil