Real-Time Imaging 3, 441-453 (1997) applications, including digital video, images, graphics and audio. These new processors employ instruction-level parallelism, which includes the superscalar and very long instruction word (VLIW) computer architectures. Intel Pentium Pro, Hewlett-Packard PA-RISC 80
An architecture for a VLSI FFT processor
β Scribed by Joseph Ja'Ja'; Robert Michael Owens
- Publisher
- Elsevier Science
- Year
- 1983
- Tongue
- English
- Weight
- 682 KB
- Volume
- 1
- Category
- Article
- ISSN
- 0167-9260
No coin nor oath required. For personal study only.
π SIMILAR VOLUMES
The RPA project aims at developing a general purpose array architecture exhibiting a wide range of perceived user parallelism. It comprises an array of efficient single-bit-slice cells, which can be configured in any number to form the processing elements of a processor array. Any number of cells i
A prototype VLSI design for a new smartcard co-processor for fast modular arithmetic with long integers is described. We present design criteria, objectives for selecting algorithms, the co-processor's structure, and some implementation details. Emphasis is also put on the manifold constraints which