An integrated co-processor architecture for a smartcard

✍ Scribed by Holger Bock; Wolfgang Mayerwieser; Karl C. Posch; Reinhard Posch; Volker Schindler

• Publisher: Elsevier Science
• Year: 1997
• Tongue: English
• Weight: 551 KB
• Volume: 20
• Category: Article
• ISSN: 1084-8045
• DOI: 10.1006/jnca.1997.0048

✦ Synopsis

A prototype VLSI design for a new smartcard co-processor for fast modular arithmetic with long integers is described. We present design criteria, objectives for selecting algorithms, the co-processor's structure, and some implementation details. Emphasis is also put on the manifold constraints which are faced when designing silicon for a smartcard, and on the optimization of algorithms in order to cope with these constraints without compromizing cryptographic strength. The co-processor is used in connection with a dedicated processor in order to make up a smartcard system capable of computing public key algorithms at top speed.