The RPA — Optimising a processor array architecture for implementation using VLSI

✍ Scribed by C.R. Jesshope

• Publisher: Elsevier Science
• Year: 1985
• Tongue: English
• Weight: 457 KB
• Volume: 37
• Category: Article
• ISSN: 0010-4655
• DOI: 10.1016/0010-4655(85)90140-7

✦ Synopsis

The RPA project aims at developing a general purpose array architecture exhibiting a wide range of perceived user parallelism.

It comprises an array of efficient single-bit-slice cells, which can be configured in any number to form the processing elements of a processor array. Any number of cells in any connected path may form a processing element, although for algorithm design and routing considerations, closed loops are the most practical topology. This paper outlines the architecture of this cell, which is considerably more efficient than the ICL DAP or GEC GRID for many word oriented operations.

This paper, also highlights the problems faced in implementing this form of architecture in silicon. The RPA architecture is therefore discussed in relation to the constraints imposed by this implementation and also in relation to the efficient realisation of multi-mode arithmetic.