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A low-resistance self-aligned T-shaped gate for high-performance sub-0.1-μm CMOS

✍ Scribed by Hisamoto, D.; Umeda, K.; Nakamura, Y.; Kimura, S.

Book ID: 114536856
Publisher: IEEE
Year: 1997
Tongue: English
Weight: 151 KB
Volume: 44
Category: Article
ISSN: 0018-9383
DOI: 10.1109/16.585550

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