A high-performance 0.25-μm CMOS technology. I. Design and characterization
✍ Scribed by Chang, W.-H.; Davari, B.; Wordeman, M.R.; Taur, Y.; Hsu, C.C.-H.; Rodriguez, M.D.
- Book ID
- 114534563
- Publisher
- IEEE
- Year
- 1992
- Tongue
- English
- Weight
- 746 KB
- Volume
- 39
- Category
- Article
- ISSN
- 0018-9383
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This paper presents the design of high-voltage NMOS and PMOS devices with shallow trench isolation (STI) in standard 0.25 mm/5 V CMOS technology. Breakdown voltages of 20 V for n-channel device with a specific on resistance of 1.06 mO cm 2 and À20 V for p-channel device with a specific on resistance
## Abstract Two 2.4‐GHz fully integrated CMOS low‐noise amplifiers (LNA) have been designed in a 0.25‐μm CMOS process. Design procedure and simulation results are presented in this paper. In the design of differential LNA, a novel idea is proposed so that the die area can be greatly reduced. © 2003