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Design and characterization of high-voltage NMOS and PMOS devices in standard 0.25 μm CMOS technology

✍ Scribed by Xiaoliang Han; Chihao Xu

Publisher: Elsevier Science
Year: 2007
Tongue: English
Weight: 281 KB
Volume: 38
Category: Article
ISSN: 0026-2692
DOI: 10.1016/j.mejo.2007.07.004

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✦ Synopsis

This paper presents the design of high-voltage NMOS and PMOS devices with shallow trench isolation (STI) in standard 0.25 mm/5 V CMOS technology. Breakdown voltages of 20 V for n-channel device with a specific on resistance of 1.06 mO cm 2 and À20 V for p-channel device with a specific on resistance of 2.83 mO cm 2 have been achieved without any modification of existing standard CMOS process.

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Design and characterization of high-voltage NMOS and PMOS devices in standard 0.25&#xa0;μm CMOS technology

✦ Synopsis

Design and characterization of high-voltage NMOS and PMOS devices in standard 0.25 μm CMOS technology