✦ LIBER ✦
Using CAD tools for shortening the design cycle of high-performance sigma–delta modulators: A 16·4 bit, 9·6 kHz, 1·71 mW ΣΔM in CMOS 0·7 μm technology
✍ Scribed by Medeiro, Fernando; Pérez-Verdú, Belén; De La Rosa, José M.; Rodríguez-Vázquez, Ángel
- Publisher
- John Wiley and Sons
- Year
- 1997
- Tongue
- English
- Weight
- 375 KB
- Volume
- 25
- Category
- Article
- ISSN
- 0098-9886
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✦ Synopsis
This paper uses a CAD methodology proposed by the authors to design a low-power second-order M. This modulator has been fabricated in a 0•7 m CMOS technology to be used as the front-end of an energy-metering mixed-signal ASIC and features 16•4 bit at a digital output rate of 9•6 kHz with a power consumption of 1•71 mW. It yields a value of the power(W)/(2 ;output rate (Hz)) figure which is the smallest reported to now, thus demonstrating the possibility to design high-performance embeddable Ms using CAD methodologies.