A 60-GHz low-noise amplifier for 60-GHz dual-conversion receiver

✍ Scribed by Yo-Sheng Lin; Simon S. Wong

• Publisher: John Wiley and Sons
• Year: 2009
• Tongue: English
• Weight: 443 KB
• Volume: 51
• Category: Article
• ISSN: 0895-2477
• DOI: 10.1002/mop.24200

✦ Synopsis

Abstract

A 60‐GHz‐band low‐noise amplifier (LNA) using bulk 65‐nm CMOS technology is reported. To achieve sufficient gain, this LNA is composed of three cascade common‐source stages followed by a cascode output stage. Current‐sharing technique is adopted in the second and third stage to reduce power dissipation. The output of each stage is loaded with an LC parallel resonance circuit to maximize the gain over the 57–64‐GHz‐band of interest. This LNA achieved input return loss (S~11~) of −10.6 to −37.4 dB, voltage gain (A~V~) of 10.7–18.8 dB, reverse isolation (S~12~) of −43.5 to −48.1 dB, input referred 1‐dB compression point (P~1dB‐in~) of −16.2 to −20.8 dBm, and input third‐order intermodulation point (IIP3) of −4 to −7.5 dBm over the 57–64‐GHz‐band of interest. It consumed only a small DC power of 21.4 mW. In addition, the chip area was only 0.849 × 0.56 mm^2^, including all the test pads and bypass capacitors. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 885–891, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24200