## Abstract A 5.2 GHz, 0.43 V voltage‐controlled oscillator (VCO) is designed and implemented in a 0.18 μm CMOS 1P6M process. The designed circuit topology consists of two parallel LC resonators in series with the gates of negative differential resistance transistors. At the supply voltage of 0.43
A 1.5-V 0.25-μm CMOS up-converter for 3–5 GHz low-power WPANs
✍ Scribed by Giuseppina Sapone; Giuseppe Palmisano
- Publisher
- John Wiley and Sons
- Year
- 2007
- Tongue
- English
- Weight
- 171 KB
- Volume
- 49
- Category
- Article
- ISSN
- 0895-2477
No coin nor oath required. For personal study only.
✦ Synopsis
Abstract
In this article, the measured performance of a 3–5 GHz low‐power up‐converter is presented. The circuit is based on a current‐reuse topology with resistive load. It was implemented in a standard low‐cost 0.25‐μm CMOS technology. The up‐converter achieves a 3.8‐dB power gain, an output 1‐dB compression point of −10.8 dBm, and a 8‐dB single‐sideband noise figure, while drawing only 2.3 mA from a 1.5‐V supply voltage. An operating bandwidth of 1.5 GHz was measured. The proposed circuit complies with the wideband/low‐power requirements of 3–5 GHz ultrawideband WPANs. © 2007 Wiley Periodicals, Inc. Microwave Opt Technol Lett 49: 2209–2212, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.22654
📜 SIMILAR VOLUMES
## Abstract In this letter, a low‐voltage and low‐power 3.5‐GHz low noise amplifier (LNA) is designed and fabricated using TSMC 0.18‐μm MS/RF complementary metal‐oxide‐semiconductor field effect transistor (CMOS) technology. The complementary current‐reused topology is utilized to achieve low dc po
## Abstract This article presents the design and the measurement results of a 3‐to 5‐GHz down‐converter fabricated in a 90‐nm CMOS technology. The circuit consists of a single‐ended low‐noise amplifier and two I/Q double‐balanced mixers. A transformer‐based on‐chip single‐ended‐to‐differential conv
## Abstract A 3–6 GHz broadband CMOS single‐ended LNA fabricated with the 0.18 μm 1P6M process for UWB and WLAN receiver is presented. Due to its noncascode circuit architecture, the proposed LNA can operate under 1V supply voltage and 6mA current consumption. In the UWB low band (3.1–5.15 GHz), th
## Abstract A concurrent 2.4/5.2‐GHz dual‐band monolithic low‐noise amplifier implemented with a 0.18‐μm mixed‐signal CMOS technology is reported for the first time. This LNA only consumed 3‐mW power, and achieved minimum noise figures of 3.3 and 3.26 dB and 2.4 and 5.2 GHz, respectively. Input and