Optimization of a very cost-effective hi
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A. PΓ©rez-TomΓ‘s; X. JordΓ ; P. Godignon
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Article
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2005
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Elsevier Science
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English
β 682 KB
This paper discusses the optimization and fabrication of a high voltage p-channel extended drain MOSFET (ED-pMOSFET) using standard low cost 2.5 lm twin-tub CMOS technology for digital applications, with only one extra processing step. The ED-pMOSFET transistor has been optimized using 2D simulators