𝔖 Bobbio Scriptorium
✦   LIBER   ✦

VIB-1 scaling limitations of P channel devices in a CMOS technology

✍ Scribed by Scott, D.B.


Book ID
114593946
Publisher
IEEE
Year
1981
Tongue
English
Weight
106 KB
Volume
28
Category
Article
ISSN
0018-9383

No coin nor oath required. For personal study only.


πŸ“œ SIMILAR VOLUMES


Optimization of a very cost-effective hi
✍ A. PΓ©rez-TomΓ‘s; X. JordΓ ; P. Godignon πŸ“‚ Article πŸ“… 2005 πŸ› Elsevier Science 🌐 English βš– 682 KB

This paper discusses the optimization and fabrication of a high voltage p-channel extended drain MOSFET (ED-pMOSFET) using standard low cost 2.5 lm twin-tub CMOS technology for digital applications, with only one extra processing step. The ED-pMOSFET transistor has been optimized using 2D simulators