Verification by Error Modeling: Using Te
โ Katarzyna Radecka, Zeljko Zilic
๐ Library
๐
2003
๐ English
โฆ LIBER โฆ
๐
Verification by Error Modeling: Using Testing Techniques in Hardware Verification (Frontiers in Electronic Testing)
โ Scribed by Katarzyna Radecka, Zeljko Zilic
- Year
- 2003
- Tongue
- English
- Leaves
- 233
- Edition
- 1
- Category
- Library
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โฆ Synopsis
This book presents the basis for reusing the test vector generation and simulation for the purpose of implementation verification, to result in a significant timesaving. It brings the results in the direction of merging manufacturing test vector generation and verification.
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