This book presents the basis for reusing the test vector generation and simulation for the purpose of implementation verification, to result in a significant timesaving. It brings the results in the direction of merging manufacturing test vector generation and verification.
Verification by Error Modeling: Using Testing Techniques in Hardware Verification (Frontiers in Electronic Testing)
โ Scribed by Katarzyna Radecka, Zeljko Zilic
- Year
- 2003
- Tongue
- English
- Leaves
- 226
- Edition
- 1
- Category
- Library
No coin nor oath required. For personal study only.
๐ SIMILAR VOLUMES
<p>1. DESIGN FLOW Integrated circuit (IC) complexity is steadily increasing. ICs incorporating hundreds of millions of transistors, mega-bit memories, complicated pipelined structures, etc., are now in high demand. For example, Intel Itanium II processor contains more than 200 million transistors, i
<p><em>Reasoning in Boolean Networks</em> provides a detailed treatment of recent research advances in algorithmic techniques for logic synthesis, test generation and formal verification of digital circuits. The book presents the central idea of approaching design automation problems for logic-level