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Two-level pipelined systolic arrays for matrix-vector multiplication

โœ Scribed by Ivan Z. Milentijevic; Igor Z. Milovanovic; Emina I. Milovanovic; Milorad B. Tosic; Mile K. Stojcev

Book ID
114288636
Publisher
Elsevier Science
Year
1999
Tongue
English
Weight
79 KB
Volume
20
Category
Article
ISSN
0920-5489

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Two-level pipelined systolic arrays for
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Novel two-level pipelined linear systolic arrays for matrix vector multiplication are proposed. The number of processing elements in the proposed arrays s reduced to half of the number of' processing elements in the existing arrays. An area-time (AT) criteria is used to compare the proposed arrays w

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The advent of VLSI technology has deeply modified the design of digital systems. The structure of special algorithms is now close to the structure of communication and computing resources on the silicon chip. Modular and regular structures allow parallel VLSI algorithms with good figures of complexi