Bit-level systolic array circuit for matrix vector multiplication
✍ Scribed by McCanny, J.V.; McWhirter, J.G.
- Book ID
- 114452188
- Publisher
- The Institution of Electrical Engineers
- Year
- 1983
- Weight
- 733 KB
- Volume
- 130
- Category
- Article
- ISSN
- 0143-7089
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📜 SIMILAR VOLUMES
Novel two-level pipelined linear systolic arrays for matrix vector multiplication are proposed. The number of processing elements in the proposed arrays s reduced to half of the number of' processing elements in the existing arrays. An area-time (AT) criteria is used to compare the proposed arrays w
This paper considers the multiplication of matrix A = (aik)n×n by vector b = (bk)n×l on the bidirectional linear systolic array (BLSA) comprised of p \_~ In/2] processing elements. To accomplish this matrix, A is partitioned into quasi-diagonal blocks. Each block contains p quasidiagonals. To avoid