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Transistor sizing for low power CMOS circuits

โœ Scribed by Borah, M.; Owens, R.M.; Irwin, M.J.


Book ID
119778049
Publisher
IEEE
Year
1996
Tongue
English
Weight
738 KB
Volume
15
Category
Article
ISSN
0278-0070

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โœ Lucas S. Heusler; Wolfgang Fichtner ๐Ÿ“‚ Article ๐Ÿ“… 1991 ๐Ÿ› Elsevier Science ๐ŸŒ English โš– 726 KB

This article describes a new method to determine the device sizes of combinational digital CMOS circuits for an upper limit on the signal propagation delays. By modeling gate delay and area or power consumption of a circuit as a simple analytical function of the device sizes, transistor sizing can b