Transistor sizing for large combinationa
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Lucas S. Heusler; Wolfgang Fichtner
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Article
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1991
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Elsevier Science
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English
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This article describes a new method to determine the device sizes of combinational digital CMOS circuits for an upper limit on the signal propagation delays. By modeling gate delay and area or power consumption of a circuit as a simple analytical function of the device sizes, transistor sizing can b