✦ LIBER ✦

A deterministic algorithm for automatic CMOS transistor sizing

✍ Scribed by Richman, B.A.; Hansen, J.E.; Cameron, K.

Book ID: 119773419
Publisher: IEEE
Year: 1988
Tongue: English
Weight: 453 KB
Volume: 23
Category: Article
ISSN: 0018-9200
DOI: 10.1109/4.1017

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

Transistor sizing for low power CMOS cir

Transistor sizing for low power CMOS circuits

✍ Borah, M.; Owens, R.M.; Irwin, M.J. 📂 Article 📅 1996 🏛 IEEE 🌐 English ⚖ 738 KB

Transistor sizing for large combinationa

Transistor sizing for large combinational digital CMOS circuits

✍ Lucas S. Heusler; Wolfgang Fichtner 📂 Article 📅 1991 🏛 Elsevier Science 🌐 English ⚖ 726 KB

This article describes a new method to determine the device sizes of combinational digital CMOS circuits for an upper limit on the signal propagation delays. By modeling gate delay and area or power consumption of a circuit as a simple analytical function of the device sizes, transistor sizing can b

A fast transistor-chaining algorithm for

A fast transistor-chaining algorithm for CMOS cell layout

✍ Hwang, C.-Y.; Hsieh, Y.-C.; Lin, Y.-L.; Hsu, Y.-C. 📂 Article 📅 1990 🏛 IEEE 🌐 English ⚖ 607 KB

A global delay model for domino cmos cir

A global delay model for domino cmos circuits with application to transistor sizing

✍ S. M. Kang; H. Y. Chen 📂 Article 📅 1990 🏛 John Wiley and Sons 🌐 English ⚖ 711 KB

A new hierarchical algorithm for transis

A new hierarchical algorithm for transistor placement in CMOS macro cell design

✍ Toshiyuki Sadakane; Hiroomi Nakao; Masayuki Terai; Kaoru Okazaki; Isao Ohkura 📂 Article 📅 2000 🏛 John Wiley and Sons 🌐 English ⚖ 494 KB 👁 1 views

We have proposed a new algorithm of transistor placement in the layout generation of CMOS macro cell design. In this algorithm, logic gates are extracted from the given net list at the transistor level and hierarchical placement is performed using it as a unit. First, for each logic gate, several ca

Cell height driven transistor sizing in

Cell height driven transistor sizing in a cell based static CMOS module design

✍ How-Rern Lin; Yu-Chin Hsu; TingTing Hwang 📂 Article 📅 1996 🏛 IEEE 🌐 English ⚖ 972 KB