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A fast transistor-chaining algorithm for CMOS cell layout

โœ Scribed by Hwang, C.-Y.; Hsieh, Y.-C.; Lin, Y.-L.; Hsu, Y.-C.


Book ID
111968072
Publisher
IEEE
Year
1990
Tongue
English
Weight
607 KB
Volume
9
Category
Article
ISSN
0278-0070

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A new hierarchical algorithm for transis
โœ Toshiyuki Sadakane; Hiroomi Nakao; Masayuki Terai; Kaoru Okazaki; Isao Ohkura ๐Ÿ“‚ Article ๐Ÿ“… 2000 ๐Ÿ› John Wiley and Sons ๐ŸŒ English โš– 494 KB ๐Ÿ‘ 1 views

We have proposed a new algorithm of transistor placement in the layout generation of CMOS macro cell design. In this algorithm, logic gates are extracted from the given net list at the transistor level and hierarchical placement is performed using it as a unit. First, for each logic gate, several ca