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Testability aspects of folded source-coupled logic

โœ Scribed by Gonzalez, J.L.; Rubio, A.


Book ID
114447616
Publisher
The Institution of Electrical Engineers
Year
1997
Tongue
English
Weight
560 KB
Volume
144
Category
Article
ISSN
1350-2409

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Modelling of source-coupled logic gates
โœ M. Alioto; G. Palumbo; S. Pennisi ๐Ÿ“‚ Article ๐Ÿ“… 2002 ๐Ÿ› John Wiley and Sons ๐ŸŒ English โš– 197 KB

## Abstract In this paper, the modelling of CMOS SCL gates is addressed. The topology both with and without output buffer is treated, and the noise margin as well as propagation delay performance are analytically derived, using standard BSIM3v3 model parameters. The propagation delay model of a si