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Leakage Current Reduction Using Subthreshold Source-Coupled Logic

✍ Scribed by Tajalli, A.; Leblebici, Y.


Book ID
115510270
Publisher
Institute of Electrical and Electronics Engineers
Year
2009
Tongue
English
Weight
414 KB
Volume
56
Category
Article
ISSN
1549-7747

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A circuit technique is proposed in this paper for simultaneously reducing the subthreshold and gate oxide leakage power consumption in domino logic circuits. PMOS-only sleep transistors and a dual threshold voltage CMOS technology are utilized to place an idle domino logic circuit into a low leakage