✦ LIBER ✦
Power-delay optimization of D-latch/MUX source coupled logic gates
✍ Scribed by M. Alioto; G. Palumbo
- Publisher
- John Wiley and Sons
- Year
- 2005
- Tongue
- English
- Weight
- 209 KB
- Volume
- 33
- Category
- Article
- ISSN
- 0098-9886
- DOI
- 10.1002/cta.305
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